Medium Speed Operation: tPHL, tPLH=75 ns (typ.) at VDD = 10 V
Buffered inputs and outputs, Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
5-V, 10-V, and 15-V parametric ratings, Noise margin (over full package-temperature range) = 1 V at VDD = 5 V 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
Standardized symmetrical output characteristics,
100% tested for quiescent current at 20 V, Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
Description
The CD4068B NAND/AND gate provides the system designer with direct implementation of the positive-logic 8-input NAND and AND functions and supplements the existing family of CMOS gates.